1. Field of the Invention
The present invention relates to a plating apparatus and a plating method for performing a plating process with a surface of a substrate such as a semiconductor substrate kept in contact with a plating liquid.
2. Description of Related Art
FIG. 4 is a schematic sectional view of a conventional plating apparatus. In FIG. 4, an electrical equivalent circuit is also shown.
The plating apparatus is adapted to perform a plating process for plating one surface of a generally round semiconductor substrate (hereinafter referred to as “wafer”) W, and includes a plating vessel 51 for containing a plating liquid, and a holder 52 for horizontally holding the wafer W.
The plating vessel 51 has a cylindrical interior surface having an inner diameter greater than the diameter of the wafer W. A disk-shaped anode 53 is horizontally disposed in the plating vessel 51 in the vicinity of the bottom of the plating vessel 51. The anode 53 has a diameter smaller than the diameter of the wafer W. The holder 52 has a ring shape as seen in plan, and is adapted to support a peripheral edge portion of the wafer W to horizontally hold the wafer W. A plurality of cathodes (not shown) are provided in the holder 52. These cathodes are brought into contact with a peripheral edge portion of a lower surface of the wafer W at positions circumferentially spaced at predetermined intervals.
The cathodes provided in the holder 52 and the anode 53 are connected to a DC power source 54. A copper seed layer is formed on the surface of the wafer W.
When the plating process is to be performed on the wafer W, the plating liquid containing copper ions is first filled in the plating vessel 51, and the wafer W is generally horizontally held by the holder 52 with the seed layer thereof facing downward. Then, the lower surface of the wafer W is brought into contact with the surface of the plating liquid filled in the plating vessel 51, and a DC voltage is applied between the anode 53 and the cathodes provided in the holder 52 by the DC power source 54. At this time, the center of the anode 53 and the center of the wafer W are generally aligned along a common vertical line. Thus, electrons are donated to copper ions in the plating liquid from the lower surface of the wafer W, so that copper atoms are deposited on the lower surface of the wafer W. In this manner, the lower surface of the wafer W is electrolytically plated.
In the plating process described above, the plating liquid is regarded, from an electrical viewpoint, as being constituted by a multiplicity of resistance components each having a resistance rc and horizontally and vertically connected to one another in a network as shown in FIG. 4. Further, the seed layer is regarded as being constituted by a plurality of resistance components each having a resistance rs and serially connected to one another between the center portion and the peripheral edge portion of the wafer.
The electric current is more liable to flow through a path having a smaller resistance between the anode 53 and the cathodes. A comparison is herein made between the resistance of an electric current path (hereinafter referred to as “first path”) extending from the center portion of the anode 53 vertically through the plating liquid to the center portion of the lower surface of the wafer W and then to the cathodes kept in contact with the peripheral edge portion of the wafer W and the resistance of an electric current path (hereinafter referred to as “second path”) extending from the peripheral edge portion of the anode 53 vertically through the plating liquid to the peripheral edge portion of the wafer W and then to the cathodes kept in contact with the peripheral edge portion of the wafer W. It is herein assumed that the plating liquid has a resistance Rc as measured vertically, and the seed layer has a resistance Rs as measured between the center portion and the peripheral edge portion of the wafer W.
In this case, the resistance of the first path is nearly equal to Rc+Rs. The resistance of the second path is nearly equal to Rc, because the electric current does not flow through the seed layer.
Since the seed layer has a small thickness, the resistance of the seed layer is not negligible. Particularly, where a minute pattern is to be formed on the wafer W, the seed layer has a very small thickness (e.g., 50 to 100 nm). Therefore, the resistances rs and Rs are increased. That is, the resistance of the first path is increased as compared with the resistance of the second path thereby to adversely influence the plating process.
Therefore, the electric current is less liable to flow through the center portion of the wafer W, and more liable to flow through the second path. In the electrolytic plating, the thickness of a film formed by the plating (plating thickness) is generally proportional to the amount of the electric current flowing from the plating liquid to the substrate. Therefore, the plating thickness is relatively small in the center portion of the wafer W and relatively thick in the peripheral edge portion of the wafer W.
In order to alleviate the non-uniformity of the plating thickness, the vertical resistance Rc of the plating liquid is increased by increasing the depth of the plating vessel 51 (a distance between the anode 53 and the wafer W) in the conventional plating apparatus. This supposedly reduces a difference in plating thickness between the center portion and the peripheral edge portion of the wafer W.
In practice, however, the electric current also flows horizontally through the plating liquid, so that the amount of the electric current flowing through the center portion of the wafer W is smaller than that calculated in consideration of the vertical resistance of the plating liquid alone. The resistance of the plating liquid as measured horizontally is regarded as the total resistance of a multiplicity of horizontal resistance components arranged depthwise of the plating vessel and connected in parallel.
As the depth of the plating vessel 51 is increased, the number of horizontal resistance components connected in parallel is increased, thereby reducing the horizontal resistance of the plating liquid. That is, the electric current is more liable to flow horizontally through the plating liquid, as the depth of the plating vessel 51 is increased. As a result, a greater amount of electric current bypasses the seed layer having a higher resistance to reach the peripheral edge portion of the wafer W.
For example, it is herein assumed that the plating liquid has a resistivity rc of 2 Ωcm and the plating vessel 51 has a depth of 20 cm. Where the plating liquid is regarded as an aggregate of liquid columns each having a 1-cm square section, the resistance rc/L of each of the liquid columns as measured laterally (horizontally) is 0.1Ω. This resistance level is virtually equivalent to the sheet resistance of the seed layer having a thickness of 100 nm. That is, the amount of the electric current flowing laterally through the plating liquid is nearly equal to the amount of the electric current flowing through the seed layer.
Where the inner diameter of the plating vessel 51 is greater than the outer size of the wafer W, an electric current flow path is established in the vicinity of the interior surface of the plating vessel 51. Therefore, the amount of the electric current flowing through the second path is further increased.
For these reasons, the difference in plating thickness between the center portion and the peripheral edge portion of the wafer W cannot be reduced to smaller than a certain level.